1. Field of the Invention
The present invention relates to random access memory and more particularly, to a resistive random access memory device.
2. Description of the Prior Art
Resistive random-access memory (RRAM) is a type of non-volatile memory that works by changing the resistance across a dielectric solid-state material. An RRAM cell stores information basically based on the resistance changing. The RRAM cell typically has two different resistance states, a low resistance state and a high resistance state. In the low resistance state (also referred to as a “LR” state or a “SET” state), it represents the RRAM cell stores a logic 1 while in the high resistance state (also referred to as a “HR” state or a “RESET” state), it represents the RRAM stores a logic 0. The RRAM cell changes its resistance states by a set operation and a reset operation. In the set operation, a large enough voltage is applied between terminals of the RRAM cell and a current flowing through the RRAM cell is simultaneously limited to a specific level. As a consequence, conductors in the RRAM cell would be formed shorted, such that the RRAM cell would be set to the low resistance state. In the reset operation, a large enough current is applied to flow through the RRAM cell and burned open the conductors (which are shorted in the set operation) in the RRAM cell. As a consequence the RRAM cell would be reset to HR state.
Please refer to FIG. 1, which illustrates the architecture of a conventional RRAM cell. An RRAM cell 10 includes a programmable resistor 40 having a resistance that is configurable by a signal SL on a source line 20, a signal BL on a bit line 50, and a signal WL on the word line 60. The signal WL is not only intended for bit selection, but also configure a turn-on resistance of the MOS switch 30 to control RRAM cell 10 at SET/RESET state.
Operations of the RRAM cell can reference to FIG. 2, which illustrates a relationship of a current (labeled with and hereinafter as “IR”) flowing through the programmable resistor 40 (from the source line 20 to bit line 50) with respect to a voltage drop (labeled with and hereinafter as “VR”) across the programmable resistor 40.
Assume RRAM cell is at low resistance state initially and BL connects to ground, when the signal SL on the source line 20 is applied to the programmable resistor 40 and increases from ground level, the current IR increases with the slope=1/(resistance at LR state) (designated with (a)) before the current IR exceeds the reset current threshold IRST. Once the current IR exceeds the reset current threshold IRST, the shorted conductors in the RRAM cell 10 would be burned opened, which changes programmable resistor 40 to HR state and current IR increases with the slope=1/(resistance at HR state) (designated with (b)).
If SL voltage is large enough to make the voltage drop VR larger than the set threshold voltage VSET of the programmable resistor 40, the conductors of programmable resistor 40 would be shorted and change to LR state. However, this high VR results a large current (designated with (c)) flowing through the LR state programmable resistor 40 and burned out the conductor again. This would force the programmable resistor back to HR state immediately and become unstable. To address this issue, the conventional RRAM cell needs one MOS switch 30 with high turn-on resistance to limit (clamp) the current level (ICLAMP) when programmable resistor 40 enter LR state during SET operation.
The above situation describe MOS switch 30 would be designed at high turn on resistance during SET mode. On the other hand, during RESET mode, MOS switch 16 should be designed low turn on resistance for larger current flowing through programmable resistor 40 and easier over IRST current. Because the MOS switch size should be fixed in RRAM cell, the turn on resistance has to be well controlled by WL voltage.
There are several drawbacks in prior art. First, to add MOS switch 30 in RRAM cell increases RRAM cell size. Second, the turn-on resistance of the MOS switch 30 need to well controlled during SET and RESET mode, however, the resistance could be varied by process variation, bias environment, and aging problem, and needs to be fine trimmed by the gate voltage of MOS switch 30 (e.g. the voltage level of the signal WL), which is not easy to be accurately controlled and needs to be calibrated chip by chip.
In light of above, it is necessary to provide a method to clamping the current flowing through the memory cell without using a MOS switch, thus addressing the above-mentioned problem.